(a) Field of the Invention
The present invention relates to a programmed circuit in a semiconductor device and, more particularly, to a programmed circuit suitably used in a redundancy circuit or switching circuit in a semiconductor memory device.
(b) Description of a Related Art
A highly integrated semiconductor memory device having a large storage capacity generally includes a redundancy circuit. The redundancy circuit is used for replacing a defective memory cell by a redundancy memory cell provided for this purpose, when the defective memory cell is detected in a product test after fabrication thereof.
The detection and replacement for the defective memory cell includes a cut-out procedure for redundancy fuses disposed in the redundancy circuit before the chip of the memory device is separated from a wafer. The cut-out of fuses is performed in a programming procedure for detecting the address of the defective memory cell replaced by the redundancy memory cell. It is necessary to secure the complete cut-out of the redundancy fuses for assuring the normal operation of the memory device.
FIG. 1 shows a conventional redundancy circuit in a DRAM 15. The redundancy circuit includes a one-shot pulse generator 19, a plurality of programmed circuits 17a to 17n each for detecting whether or not an input address signal specifies the address of a defective memory cell in a regular memory cell array 16a, a redundancy memory driver 18, an AND gate AND1 for receiving an input from each of the programmed circuits 17a to 17n and the redundancy memory driver 18. The DRAM 15 further includes an X-decoder 16c, Y-decoder 16d, a regular memory cell array 16a and a redundancy memory cell array 16b.
FIG. 2A shows an example of the programmed circuit shown in FIG. 1, and FIG. 2B shows one of the programmed branches shown in FIG. 2A. The programmed circuit 12 of FIG. 2A includes a number of programmed branches 11 shown in FIG. 2B corresponding to the number of bits of the address signal used in the memory device. In FIG. 2B, a p-ch precharge transistor p11 is turned on during a precharge period by a precharge signal supplied as a one-shot pulse to charge a node "C". Node "C" is discharged or not discharged in a subsequent detection period, through an n-ch transistor "n11" receiving an enable signal, depending on the on-state (non-cut) or off-state (cut-out) of the fuse F11. The potential of node "C" is detected as a result signal, which represents the cut-out or non-cut of the fuse F11.
The programmed circuit 12 shown in FIG. 2A is supplied with an input address signal including bits A0 to A3 as well as A0B to A3B, wherein "B" in A0B to A3B means "NOT" of the bits A0 to A3. If the programmed circuit 12 detects a defective address from the input address signal, the programmed circuit 12 replaces the input address by a redundancy address, thereby replacing the defective memory cell by the redundancy memory cell.
In the programmed circuit 12 of FIG. 2A, if the corresponding bit of A0 to A3 and A0B to A3B assumes a high level, the corresponding node "C" assumes a low level or a high level depending on the cut-out or non-cut of the fuses. On the other hand, if the fuse is incompletely cut to have an intermediate resistance between the off-sate and the on-state of the fuse, it takes a long time for the potential of node "C" to fall from the high level to a low level in the detection period. This causes a larger time length consumed for the detection and thus involves a lower operational speed of the memory device, or causes a failure in the detection period.
Such an incomplete cut-out in the redundancy circuit is increasing along with the increase of the number of redundancy fuses in the recent memory device. Especially in the DRAMs having a large storage capacity and having a multi-level interconnection structure, since the redundancy fuses are generally implemented by a silicide layer disposed as an underlying interconnect layer, the complete cut-out is difficult to achieve. So is the case of the redundancy fuses implemented by a metallic layer such as an aluminum layer.
FIGS. 3A and 3B are a top plan view and a sectional view, respectively, of a redundancy fuse before cut-out of the redundancy fuse, whereas FIGS. 3C and 3D are top plan view and a sectional view corresponding to FIGS. 2A and 2B, respectively, after the cut-out of the redundancy fuse for showing the problem of the incomplete cut-out.
As shown in FIG. 3B, the redundancy fuse 13b is irradiated by a laser beam through a window 14 formed in a cover film 13c covering a wafer 13. If the irradiated and evaporated portion of the redundancy fuse 13b is re-coagulated at the bottom of the etched portion of the window 14, or if the bottom portion of a thick redundancy fuse 13b is not completely evaporated, as shown in FIGS. 3C and 3D, the re-coagulated portion or remaining portion (referred to simply as a remaining portion) 13g may bridge the cut-out part of the fuse 13b. The remaining portion 13g generally has a resistance higher than the original resistance of the fuse 13b by several tens or a hundred times.
In another case, if the redundancy fuse is implemented by a metallic film generally having a higher reflective index, the metallic film reflects most part of the irradiated laser beam and may leave a remaining portion, and thus is difficult to achieve a complete cut-out. This is especially true in the case of a redundancy fuse implemented by a contact plug 13f made of tungsten and connecting interconnect layers 13e and 13d, such as shown in FIGS. 3E and 3F showing sectional views before and after, respectively, the cut-out of the redundancy fuse 13f. This is because the tungsten has a different heat absorption rate from that of aluminum etc.
A technique for solving the problem incomplete cut-out is described in Patent Publication JP-A-64-67798. FIG. 4 shows the improved programmed circuit in the redundancy circuit described therein. In the redundancy circuit shown in FIG. 4, the programmed circuit 17 for a single bit of the address signal has a fuse F12 which is programmed depending on the data stored, a flip-flop circuit FF12 outputting a data depending on the programming of the fuse F12 when an enable signal is input, and an output section 17a implemented by a pair of transfer gates G1 and G2 for receiving corresponding bit signals A0 and A0B, for example, of an input address for delivering a detection signal of the bit.
In this configuration, the flip-flop circuit FF12 delivers a stable output corresponding to the cut-out or non-cut of the fuse F12 irrespective of the incomplete cut-out of the fuse F12, although the flip-flop FF12 has a some delay in delivering a correct output in the case of incomplete cut-out.
In a conventional memory device, it is generally desired that the circuit area for the redundancy circuit be reduced. In this respect, it is desirable that the one-shot pulse generator provided for each decoder circuit in the conventional memory device be deleted. In addition, in the proposed programmed circuit, the delay which may appear in the flip-flop circuit FF12 in the case of the incomplete cut-out involves a difficult setting for the delay time in the redundancy circuit.